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june 2009 doc id 15797 rev 1 1/37 37 LIS302DLH mems digital output motion sensor ultra low-power high performance 3-axes ?piccolo? accelerometer features wide supply voltage, 2.16 v to 3.6 v low voltage compatible ios, 1.8 v ultra thickness 0.8 mm ultra low-power mode consumption down to 10 a 2 g /4 g / 8 g dynamically selectable full-scale i 2 c/spi digital output interface 16 bit data output 2 independent programmable interrupt generators for free-fall and motion detection sleep to wake-up function 6d orientation detection embedded self-test 10000 g high shock survivability ecopack ? rohs and ?green? compliant (see section 8 ) applications motion activated functions free-fall detection intelligent power saving for handheld devices pedometer display orientation gaming and virtual reality input devices impact recognition and logging vibration monitoring and compensation description the LIS302DLH is an ultra low-power high performance three axes linear accelerometer belonging to the ?picco lo? family, with digital i 2 c/spi serial interface standard output. the device features ultra low-power operational modes that allow advanced power saving and smart sleep to wake-up functions. the LIS302DLH has dynamically user selectable full scales of 2 g /4 g /8 g and it is capable of measuring accelerations with output data rates from 0.5 hz to 1 khz. the self-test capability a llows the user to check the functioning of the sensor in the final application. the device may be configured to generate interrupt signal by inertial wake-up/free-fall events as well as by the position of the device itself. thresholds and timing of interrupt generators are programmable by the end user on the fly. the LIS302DLH is available in small thin plastic land grid array package (lga) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c. lga-14 (3x5x0.8mm) table 1. device summary order codes temperature range [ c] package packaging LIS302DLH -40 to +85 lga-14 tray LIS302DLHtr -40 to +85 lga-14 tape and reel www.st.com
contents LIS302DLH 2/37 doc id 15797 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.4 sleep to wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LIS302DLH contents doc id 15797 rev 1 3/37 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27 7.5 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7 hp_filter_reset (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8 reference (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.10 out_x_l (28h), out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.11 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.12 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13 int1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 int1_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15 int1_ths (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.16 int1_duration (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.17 int2_cfg (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.18 int2_src (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.19 int2_ths (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.20 int2_duration (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables LIS302DLH 4/37 doc id 15797 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted . . . . . . . . . . 6 table 4. electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted . . . . . . . . . . . . 7 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 16 table 14. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 16 table 15. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 18. ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 22 table 20. normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 22 table 21. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 22. ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 23. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 24. high-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 25. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 26. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 27. data signal on int 1 and int 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 28. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 29. ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 30. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 31. ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 32. sleep to wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 33. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 34. reference description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 35. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 36. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 37. int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 38. int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 39. interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 40. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 41. int1_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 42. int1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 43. int1_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 44. int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 45. int1_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 46. int2_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 48. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 47. int2_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LIS302DLH list of tables doc id 15797 rev 1 5/37 table 49. int2_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 50. int2_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 51. int2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 52. int2_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 53. int2_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 54. int2_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of figures LIS302DLH 6/37 doc id 15797 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. LIS302DLH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. lga-14: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LIS302DLH block diagram and pin description doc id 15797 rev 1 7/37 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection charge amplifier y+ z+ y- z- a x+ x- i2c spi cs scl/spc sda/sdo/sdi sdo / sa0 control logic & interrupt gen. int 1 clock trimming circuits reference self test control logic a/d converter int 2 mux 1 13 8 6 1 bottom view 13 8 6 top view x z y
block diagram and pin description LIS302DLH 8/37 doc id 15797 rev 1 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 gnd 0v supply 3 reserved connect to vdd 4 gnd 0v supply 5 gnd 0v supply 6 vdd power supply 7cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 8 int1 inertial interrupt 1 9 int2 inertial interrupt 2 10 gnd 0v supply 11 reserved connect to gnd 12 sdo spi serial data output i 2 c less significant bit of the device address 13 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 14 scl spc i 2 c serial clock (scl) spi serial port clock (spc)
LIS302DLH mechanical and electrical specifications doc id 15797 rev 1 9/37 2 mechanical and electrical specifications 2.1 mechanical characteristics table 3. mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit fs measurement range (3) fs bit set to 00 2.0 g fs bit set to 01 4.0 fs bit set to 11 8.0 so sensitivity fs bit set to 00 12 bit representation 0.911.1 m g /digit fs bit set to 01 12 bit representation 1.822.2 fs bit set to 11 12 bit representation 3.5 3.9 4.3 tcso sensitivity change vs temperature fs bit set to 00 0.01 %/c ty o f f typical zero- g level offset accuracy (4),(5) fs bit set to 00 20 m g tcoff zero- g level change vs temperature max delta from 25 c 0.1 m g /c an acceleration noise density fs bit set to 00 218 g/ vst self-test output change (6),(7),(8) fs bit set to 00 x axis 120 300 550 lsb fs bit set to 00 y axis 120 300 550 lsb fs bit set to 00 z axis 140 350 750 lsb top operating temperature range -40 +85 c wh product weight 20 mgram 1. the product is factory calibrated at 2.5 v. the operat ional power supply range is from 2.16 v to 3.6 v. 2. typical specificat ions are not guaranteed 3. verified by wafer level test and measur ement of initial offset and sensitivity 4. typical zero- g level offset value after msl3 preconditioning 5. offset can be eliminated by enabl ing the built-in high pass filter 6. the sign of ?self-test output change? is defined by ctrl_reg4 stsign bit ( table 28 ), for all axes. 7. self-test output changes with the power supply. ?self-test output change? is defined as output[lsb] (ctrl_reg4 st bit=1) - output[lsb] (ctrl_reg4 st bit=0) . 1lsb=4 g /4096 at 12bit representation, 2 g full-scale 8. output data reach 99% of final value after 3/odr when enabling self-test mode, due to device filtering hz
mechanical and electrical specifications LIS302DLH 10/37 doc id 15797 rev 1 2.2 electrical characteristics table 4. electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 2.16 2.5 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idd current consumption in normal mode 250 a iddlp current consumption in low-power mode 10 a iddpdn current consumption in power-down mode 1a vih digital high level input voltage 0.8*vdd_io v vil digital low level input voltage 0.2*vdd_io v voh high level output voltage 0.9*vdd_io v vol low level output voltage 0.1*vdd_io v odr output data rate in normal mode dr bit set to 00 50 hz dr bit set to 01 100 dr bit set to 10 400 dr bit set to 11 1000 odr lp output data rate in low-power mode pm bit set to 010 0.5 hz pm bit set to 011 1 pm bit set to 100 2 pm bit set to 101 5 pm bit set to 110 10 bw system bandwidth (4) odr/2 hz ton turn-on time (5) odr = 100 hz 3/odr s top operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5 v. the oper ational power supply range is from 2.16 v to 3.6 v. 2. typical specification are not guaranteed 3. it is possible to remove vdd maintaining vdd_io withou t blocking the communication busse s, in this condition the measurement chain is powered off. 4. refer to table 20 for filter cut-off frequency 5. time to obtain valid data after exiting power-down mode
LIS302DLH mechanical and electrical specifications doc id 15797 rev 1 11/37 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (a) 3. when no communication is on-going, data on cs, spc, sdi and sdo are driven by internal pull-up resistors table 5. spi slave timing values symbol parameter value (1) unit min. max. tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 6 tdis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock fr equency for spi with both 4 and 3 wires, based on characterization results, not tested in production a. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output port spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
mechanical and electrical specifications LIS302DLH 12/37 doc id 15797 rev 1 2.3.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (b) table 6. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production 2. cb = total capacitance of one bus line, in pf b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both port sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop star t
LIS302DLH mechanical and electrical specifications doc id 15797 rev 1 13/37 2.4 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only a nd functional operation of the device under these conditions is not implied. ex posure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 6.0 v table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to 6 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3000 g for 0.5 ms 10000 g for 0.1 ms a unp acceleration (any axis, unpowered) 3000 g for 0.5 ms 10000 g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4 (hbm) kv 1.5 (cdm) kv 200 (mm) v this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part this is an esd sensitive device, improper handling can cause permanent damages to the part
mechanical and electrical specifications LIS302DLH 14/37 doc id 15797 rev 1 2.5 terminology 2.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. as the sensor can measure dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g in x axis and 0 g in y axis whereas the z axis will measure 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (t yoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 2.5.3 self-test self-test allows to check the sensor functionality without moving it. the self-test function is off when the self-test bit (st) of ctrl_reg4 (control register 4) is programmed to ?0?. when the self-test bit of ctrl_reg4 is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when self-test is activat ed, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signal s change within the amplitude specified inside table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2.5.4 sleep to wake-up the ?sleep to wake-up? function, in conjunct ion with low-power mode, allows to further reduce the system power consumption and develop new smart applications. LIS302DLH may be set in a low-power operating mode, characterized by lower date rates refreshments. in this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests. when the ?sleep to wake-up? function is activated, LIS302DLH is able to automatically wake-up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system may be efficiently switched from low-power mode to full- performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
LIS302DLH functionality doc id 15797 rev 1 15/37 3 functionality the LIS302DLH is a nano, low-power, digital output 3-axis linear accelerometer packaged in a lga package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures whic h are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is in the ff range. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS302DLH features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. the LIS302DLH may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. both free-fall and wake-up can be available simultaneously on two different pins. 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (tyoff). the trimming values are stored inside the device in a non volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. this allows to use the device without further calibration.
application hints LIS302DLH 16/37 doc id 15797 rev 1 4 application hints figure 5. LIS302DLH electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to the pin 6 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to remo ve vdd maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high. the functions, the threshold and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i 2 c/spi interface. 4.1 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020c. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com . 6 8 13 1 top view cs 10uf vdd 100nf gnd vdd_io sdo sda/sdi/sdo int 1 int 2 scl/spc digital signal from/to signal controller.signal?s levels are defined by proper selection of vdd_io 1 13 8 6 top view x z y directions of the detectable accelerations
LIS302DLH digital interfaces doc id 15797 rev 1 17/37 5 digital interfaces the registers embedded inside the LIS302DLH may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high (i.e. connected to vdd_io). 5.1 i 2 c serial interface the LIS302DLH i 2 c is a bus slave. the i 2 c is employed to write da ta into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LIS302DLH. when the bus is free both the lines are high. the i 2 c interface is compliant wit h fast mode (400 khz) i 2 c standards as well as with the normal mode. table 8. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0 sdo i 2 c less significant bit of the device address (sa0) spi serial data output (sdo) table 9. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces LIS302DLH 18/37 doc id 15797 rev 1 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS302DLH is 001100xb. sdo / sa0 pad can be used to modify less significant bit of the device address. if sa0 pad is connected to voltage supply, lsb is ?1? (address 0011001b) else if sa0 pad is connected to ground, lsb value is ?0? (address 0011000b). this solution permits to connect and address two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LIS302DLH behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, a 8-bit sub-address (sub ) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is ?1?, the sub (r egister address) is automatically increased to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the tw o sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 10 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 10. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
LIS302DLH digital interfaces doc id 15797 rev 1 19/37 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the LIS302DLH spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . table 12. transfer when master is writing multiple bytes to slave: master st sad + w sub data data sp slave sak sak sak sak table 13. transfer when master is receiving (reading) one byte of data from slave: master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 14. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces LIS302DLH 20/37 doc id 15797 rev 1 figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multip le bytes read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last fa lling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain un changed in multiple read/write commands. when 1, the address is auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further bl ocks of 8 clock peri ods will be added. when ms bit is ?0? the address used to read/write data remains the same for every block. when ms bit is ?1? the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 5.2.1 spi read figure 7. spi read protocol cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7do6do5do4do3do2do1do0 ms cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
LIS302DLH digital interfaces doc id 15797 rev 1 21/37 the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. figure 8. multiple bytes spi read protocol (2 bytes example) 5.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 cl ock pulses. multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the da ta that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. cs spc sdi sdo rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms
digital interfaces LIS302DLH 22/37 doc id 15797 rev 1 figure 10. multiple bytes spi write protocol (2 bytes example) 5.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to ?1? bit sim (spi serial interface mode selection) in ctrl_reg4. figure 11. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
LIS302DLH register mapping doc id 15797 rev 1 23/37 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. table 15. register address map name type register address default comment hex binary reserved (do not modify) 00 - 0e reserved who_am_i r 0f 000 1111 00110010 dummy register reserved (do not modify) 10 - 1f reserved ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 ctrl_reg4 rw 23 010 0011 00000000 ctrl_reg5 rw 24 010 0100 00000000 hp_filter_reset r 25 010 0101 dummy register reference rw 26 010 0110 00000000 status_reg r 27 010 0111 00000000 out_x_l r 28 010 1000 output out_x_h r 29 010 1001 output out_y_l r 2a 010 1010 output out_y_h r 2b 010 1011 output out_z_l r 2c 010 1100 output out_z_h r 2d 010 1101 output reserved (do not modify) 2e - 2f reserved int1_cfg rw 30 011 0000 00000000 int1_source r 31 011 0001 00000000 int1_ths rw 32 011 0010 00000000 int1_duration rw 33 011 0011 00000000 int2_cfg rw 34 011 0100 00000000 int2_source r 35 011 0101 00000000 int2_ths rw 36 011 0110 00000000 int2_duration rw 37 011 0111 00000000 reserved (do not modify) 38 - 3f reserved
register description LIS302DLH 24/37 doc id 15797 rev 1 the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered-up. 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 who_am_i (0fh) device identification register. this register contains the device identifier that for LIS302DLH is set to 32h. 7.2 ctrl_reg1 (20h) pm bits allow to select between power-down and two operating active modes. the device is in power-down mode when pd bits are set to ?000? (default value after boot). table 19 shows all the possible power mode configurations and respective output data rates. output table 16. who_am_i register 00110010 table 17. ctrl_reg1 register pm2 pm1 pm0 dr1 dr0 zen yen xen table 18. ctrl_reg1 description pm2 - pm0 power mode selection. default value: 000 (000: power-down; others: refer to table 19 ) dr1, dr0 data rate selection. default value: 00 (00:50 hz; others: refer to table 20 ) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled)
LIS302DLH register description doc id 15797 rev 1 25/37 data in the low-power modes are computed with low-pass filter cut-off frequency defined by dr1, dr0 bits. dr bits, in the normal-mode operation, select the data rate at which acceleration samples are produced. in low-power mode they define the output data resolution. table 20 shows all the possible configuration for dr1 and dr0 bits. 7.3 ctrl_reg2 (21h) table 19. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 0 0 0 power-down -- 0 0 1 normal mode odr 0 1 0 low-power 0.5 0 1 1 low-power 1 1 0 0 low-power 2 1 0 1 low-power 5 1 1 0 low-power 10 table 20. normal-mode output data rate configurations and low-pass cut-off frequencies dr1 dr0 output data rate [hz] odr low-pass filter cut-off frequency [hz] 00 50 37 01 100 74 1 0 400 292 1 1 1000 780 table 21. ctrl_reg2 register boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 table 22. ctrl_reg2 description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) hpm1, hpm0 high pass filter mode selection. default value: 00 (00: normal mode; others: refer to table 23 ) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register)
register description LIS302DLH 26/37 doc id 15797 rev 1 boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. hpcf[1:0] . these bits are used to configure high-pass filter cut-off frequency f t which is given by: the equation can be simplified to the following approximated equation: hpen2 high pass filter enabled for interrupt 2 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpen1 high pass filter enabled for interrupt 1 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpcf1, hpcf0 high pass filter cut-off frequency configuration. default value: 00 (00: hpc=8; 01: hpc=16; 10: hpc=32; 11: hpc=64) table 23. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode (reset reading hp_reset_filter) table 24. high-pass filter cut-off frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 table 22. ctrl_reg2 description (continued) f t 1 1 hpc ----------- - ? ?? ?? f s 2 ------ ? ln = f t f s 6hpc ? ---------------------- =
LIS302DLH register description doc id 15797 rev 1 27/37 7.4 ctrl_reg3 [interrupt ctrl register] (22h) 7.5 ctrl_reg4 (23h) table 25. ctrl_reg3 register ihl pp_od lir2 i2_cfg1 i2_cfg0 lir1 i1_cfg1 i1_cfg0 table 26. ctrl_reg3 description ihl interrupt active high, low. default value: 0 (0: active high; 1:active low) pp_od push-pull/open drain selection on interrupt pad. default value 0. (0: push-pull; 1: open drain) lir2 latch interrupt request on int2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i2_cfg1, i2_cfg0 data signal on int 2 pad control bits. default value: 00. (see table below) lir1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i1_cfg1, i1_cfg0 data signal on int 1 pad control bits. default value: 00. (see table below) table 27. data signal on int 1 and int 2 pad i1(2)_cfg1 i1(2)_cfg0 int 1(2) pad 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running table 28. ctrl_reg4 register bdu ble fs1 fs0 stsign 0 st sim
register description LIS302DLH 28/37 doc id 15797 rev 1 bdu bit is used to inhibit output registers update between the reading of upper and lower register parts. in default mode (bdu = ?0?) the lower and upper register parts are updated continuously. if it is not sure to read faster than output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output registers is not updated until the upper (lower) part is read too. this feature avoids reading lsb and msb related to different samples. 7.6 ctrl_reg5 (24h) turnon bits are used for turning on the sleep to wake function. setting turnon[1:0] bits to 11 the ?sleep to wake? function is enabled. when an interrupt event occurs the device is turned to normal mode increasing the odr to the value defined in table 29. ctrl_reg4 description bdu block data update. default value: 0 (0: continuos update; 1: output register s not updated between msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1, fs0 full-scale selection. default value: 00. (00: 2 g ; 01: 4 g ; 11: 8 g ) stsign self-test sign. default value: 00. (0: self-test plus; 1 self-test minus) st self-test enable. default value: 0. (0: self-test disabled; 1: self-test enabled) sim spi serial interface mode selection. default value: 0. (0: 4-wire interface; 1: 3-wire interface) table 30. ctrl_reg5 register 000000turnon1turnon0 table 31. ctrl_reg5 description tu r n o n 1 , tu r n o n 0 turn-on mode selection for sleep to wake function. default value: 00. table 32. sleep to wake configuration turnon1 turnon0 sleep to wake status 0 0 sleep to wake function is disabled 11 turned on: the device is in lo w power mode (odr is defined in ctrl_reg1)
LIS302DLH register description doc id 15797 rev 1 29/37 ctrl_reg1. although the device is in normal mode, ctrl_reg1 content is not automatically changed to ?normal mode? configuration. 7.7 hp_filter_reset (25h) dummy register. reading at this address zeroes instantaneously the content of the internal high pass-filter. if the high pass filter is enabled all three axes are instantaneously set to 0 g. this allows to overcome the settling time of the high pass filter. 7.8 reference (26h) this register sets the acceleration value taken as a reference for the high-pass filter output. when filter is turned on (at least one of fds, hpen2, or hpen1 bit is equal to ?1?) and hpm bits are set to ?01?, filter out is generated taking this value as a reference. 7.9 status_reg (27h) table 33. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 34. reference description ref7 - ref0 reference value for high-pass filter. default value: 00h. table 35. status_reg register zyxor zor yor xor zyxda zda yda xda table 36. status_reg description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the pr evious one before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the z-axis has overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the x-axis has overwritten the previous one)
register description LIS302DLH 30/37 doc id 15797 rev 1 7.10 out_x_l (28h), out_x_h (29h) x-axis acceleration data. the value is expressed as two?s complement. 7.11 out_y_l (2ah), out_y_h (2bh) y-axis acceleration data. the value is expressed as two?s complement. 7.12 out_z_l (2ch), out_z_h (2dh) z-axis acceleration data. the value is expressed as two?s complement. 7.13 int1_cfg (30h) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: a new data for the z-axis is not yet available; 1: a new data for the z-axis is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available; 1: a new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: a new data for the x-axis is available) table 36. status_reg description (continued) table 37. int1_cfg register aoi 6d zhie zlie yhie ylie xhie xlie table 38. int1_cfg description aoi and/or combination of interrupt events. default value: 0. (see table 39 ) 6d 6 direction detection function enable. default value: 0. (see table 39 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
LIS302DLH register description doc id 15797 rev 1 31/37 configuration register for interrupt 1 source. 7.14 int1_src (31h) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 39. interrupt 1 source configurations aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 38. int1_cfg description table 40. int1_src register 0 ia zhzlyhylxhxl table 41. int1_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred)
register description LIS302DLH 32/37 doc id 15797 rev 1 interrupt 1 source register. read only register. reading at this address clears int1_src ia bit (and the interrupt signal on int 1 pin) and allows the refreshment of data in the int1_src register if the latched option was chosen. 7.15 int1_ths (32h) 7.16 int1_duration (33h) d6 - d0 bits set the minimum duration of the interrupt 1 event to be recognized. duration steps and maximum values depend on the odr chosen. 7.17 int2_cfg (34h) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 41. int1_src description table 42. int1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 43. int1_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 44. int1_duration register 0 d6d5d4d3d2d1d0 table 45. int1_duration description d6 - d0 duration value. default value: 000 0000 table 46. int2_cfg register aoi 6d zhie zlie yhie ylie xhie xlie
LIS302DLH register description doc id 15797 rev 1 33/37 configuration register for interrupt 2 source. 7.18 int2_src (35h) table 47. int2_cfg description aoi and/or combination of interrupt events. default value: 0. (see table below) 6d 6 direction detection function enable. default value: 0. (see table below) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 48. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 49. int2_src register 0 ia zhzlyhylxhxl
register description LIS302DLH 34/37 doc id 15797 rev 1 interrupt 2 source register. read only register. reading at this address clears int2_src ia bit (and the interrupt signal on int 2 pin) and allows the refreshment of data in the int2_src register if the latched option was chosen. 7.19 int2_ths (36h) 7.20 int2_duration (37h) d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. table 50. int2_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 51. int2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 52. int2_ths description ths6 - ths0 interrupt 2 threshold. default value: 000 0000 table 53. int2_duration register 0 d6d5d4d3d2d1d0 table 54. int2_duration description d6 - d0 duration value. default value: 000 0000
LIS302DLH package information doc id 15797 rev 1 35/37 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 12. lga-14: mechanical data and package dimensions outline and mechanical data lga-14 (3x5x0.8mm)
revision history LIS302DLH 36/37 doc id 15797 rev 1 9 revision history table 55. document revision history date revision changes 04-jun-2009 1 initial release
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